EECS151 Tapeout (Fall 2024)

The EECS151 Tapeout Decal

Contact: 151-tapeout-decal@lists.berkeley.edu

This project-based course is a follow up to EECS 151: Introduction to Digital Design and Integrated Circuits, where students learn principles, components, and methodologies for large scale digital system design. Students who designed a CPU core in the EECS151 ASIC (application specific integrated circuits) lab integrate their core into a larger System-on-Chip (SoC) using agile hardware design tools such as Chipyard and Chisel, a hardware construction language. While covering the basics of VLSI flows and parameterizable computer architecture, the course focuses on a very hands-on approach and aims to tapeout an SoC utilizing the EECS151 cores by end of semester.

Get involved! Fill out https://berkie.ee/eecs151-tapeout-join or reach out to us at the email address above!



Enrolling in EECS151 Tapeout

Students who are interested in signing up for the Decal in Fall 2024 should fill out this enrollment form to recieve a permission code (they will be distributed in batches, first-come-first-serve). Our DeCal listing from Fall '24 is https://decal.studentorg.berkeley.edu/courses/7534 .

Please email us if you are a concurrent enrollment student- we prioritize matriculated UC Berkeley students. Space permitting, however, concurrent enrollment students are welcome to take HOPE.

Classes begin week of 9/5.



Pre-requisites

This rigorous course is designed for students who have completed EECS 151 LA ASIC and/or EE 194/290C (the traditional 'Tapeout' and 'Bringup' courses). Students who instead completed EECS 151 LB FPGA are welcome but may have a higher learning curve and will be working with the cores of ASIC students. Students who have not completed EECS 151 or Tapeout/Bringup are recommended to take this Decal after having completed the course. Those unsure are welcome to email us. We are extremely welcoming to self-motivated students of various backgrounds but do wish to emphasize that background knowledge will be helpful, especially as this is the first iteration of the course.



Course Structure

This course spans 13 weeks. Class meets for two hours once a week. Each class begins with a short mini lecture, overview of project status, and check-ins with each team on milestones and obstacles. Students are expected to spend a bit more time each week outside of class time working on their project. There will be a presentation and tapeout poster at the end of the semester - and possibly a SKY130 tapeout.

Work Sessions

We may have work and "office hours" sessions. You can also organize your own work sessions. We will use this calendar to track them.

Class calendar: http://berkie.ee/tapeoutcalendar



Other Resources

bCourses will be available. We will keep track of grade-related things mostly in Gradescope. Other course content will be found here on the website and on Github. When in doubt, ask on the Discord: https://discord.gg/DXbg598wcR



The Complete Syllabus

..can be found here (Fall 2024)! Check it out for all your grading and policy questions.

Instructors
Elam
Elam Day-Friedland [image pending]

Lucy
Lucy Revina

Course Schedule
Week Topic Reference Lab Lab Checkoff Due Project Checkpoint
1
9/5 		What does it mean to tapeout a chip?

  • Introduction to course goals and project expectations
  • A crash course review on VLSI and Hammer as it relates to the EECS151 Tapeout
  • Self-introductions and project discussion
Lab Manual (Do Lab 1)

Prelab: Gitlab (Github Classroom) Lab: Chipyard Setup (Github Classroom) 		Get on the Gradescope (code on Discord.)
2
9/12 		Chipyard Crash Course and Setup

  • Crash course the basics of hardware generation as it relates to the EECS151 Tapeout
  • Overview of current work on the EECS151 Tapeout Chipyard
  • Repository setup for the EECS151 Tapeout and repo exploration homework
Lab Manual (Do Lab 2)

Lab 2 in the lab manual 		Import your core and create a Verilog black box.
3
9/19 		Part 1: MMIO, TileLink, and Diplomacy

  • Overview of more advanced concepts in Chipyard as they relate to the EECS151 Tapeout
  • Make sure we have a working blackbox
Lab Manual (Continuing Lab 2)

 Create a TileLink Tile and single-core Chipyard config. Write your first ChiselTest for it. (Just kidding, we are a bit delayed.)
4
9/26 		Part 2: MMIO, TileLink, and Diplomacy

  • First presentation and check-ins (just kidding)
  • Create a TileLink Tile and get started on the FSM interface.
Lab Manual (Not yet posted, my bad)

 Present your current work so far, what your goals are for your subteam, and what you think we should delve more into. Start connecting your core to the rest of the SoC. (Just kidding, we are a bit delayed.)
5
10/3 		Regmaps and Interfaces

  • Writing register maps in Chisel and understand MMIO as a strong abstraction
  • Understand how to mate interfaces (TLWidth nodes, breaking up memory ops etc)
Lab Manual

 Make sure your core is connected to the rest of the SoC.
6
10/10 		Core Modifications

  • What improvements to the EECS151 core might enable better functionality, such as running Linux?
  • Interrupt handling, etc
Lab Manual

 If there's time, modify your core to be able to handle interrupts.
7
10/17 		Simulation and Verification

  • Verification at the SoC level in contrast to EECS151
  • Unit tests, system tests, C tests, built-in tests..
Lab Manual

 Make sure your design is functional and robust!
8
10/24 		Midterm Presentation

  • Larger updates from teams focused on the timeline for final deliverables, project scoping, and what teams may need from each other - complete slide decks required
  • Coordinate integration plans
Lab Manual

 Prepare for integration.
9
10/31 		Start Integration

  • Top-level integration and flows
  • Integration testing
Lab Manual

 Integrate integrate integrate!
10
11/7 		Custom and Auxiliary Extensions [If Time]

  • If all goes extraordinarily smoothly, there may be time to attempt integrating an accelerator, extra peripherals, or other adventures of choice
Lab Manual

 Students' choice.
11
11/14 		Buffer Week

  • The final rush to make sure everyone’s work is properly interfacing together
Lab Manual

 -
12
11/21 		Physical Design and Final Integration

  • The joys and pains of Place-and-Route, at the SoC level
  • The importance of DRC and LVS when taping out
Lab Manual

 Run the SoC through the complete flow, solving any DRC and LVS issues.
13
11/28 		Last Project Week!

  • Do whatever it takes to get the SoC tapeout-ready!
Lab Manual

 Get DRC and LVS clean!